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| ac SEPTEMBER 2001 XRT71D03 3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR REV. 1.2.0 GENERAL DESCRIPTION The XRT71D03 is a three channel, single chip Jitter Attenuator, that meets the Jitter transfer characteristics requirements specified in the ETSI TBR-24, Bellcore GR-499 and GR-253 standards. In addition, the XRT71D03 also meets the Jitter and Wander specifications described in the ANSI T1.105.03b 1997, Bellcore GR-253 and GR-499 standards. FEATURES * Meets the E3/DS3/STS-1 jitter requirements * No external components required * Compliant with jitter transfer template outlined in ITU G.751, G.752, G.755, GR-235-CORE, GR499-CORE,1995 standards FIGURE 1. BLOCK DIAGRAM OF THE XRT71D03 * Meets output jitter requirement as specified by ETSI TBR24 * Meets the Jitter and Wander specifications described in T1.105.03b,GR-253 and GR-499 standards. * Selectable buffer size of 16 and 32 bits * Jitter attenuator can be disabled * Available in a 64 pin LQFP package. * Single 3.3V or 5.0V supply. * Operates over - 40 C to 85 C temperature range. APPLICATIONS * E3/DS3 Access Equipment. * DSLAMs MCLK_n Timing Control Block Phase locked Loop ICT DJA_n RClk_n RClkES RPOS_n RNEG_n FSS Write Clock Read Clock STS1_n DS3/E3_n RRCLK_n RRPOS_n 16/32 Bit FIFO RRNEG_n FL_n RRCLKES Channel 0 Channel 1 Channel 2 MODE_CTRL HOST Reset Microprocessor Serial Interface XRT71D03 n = 0, 1, 2 CS SDI SDO SClk Exar Corporation 48720 Kato Road, Fremont CA, 94538 * (510) 668-7000 * FAX (510) 668-7017 * www.exar.com XRT71D03 3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR REV. 1.2.0 ac FIGURE 2. PIN OUT OF THE XRT71D03 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 AVDD GND RRCLK_1 RRPOS_1 RRNEG_1 RCLKES NC VDD DS3/E3_2 SDO FSS RRNEG_2 RRPOS_2 RRCLK_2 GND AVDD PART NUMBER XRT71D03IV AVDD GND RRCLK_0 RRPOS_0 RRNEG_0 RRCLKES NC Reset DS3/E3_1 VDD MODE_CTRL ICT HOST FLRST GND NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 AGND FL1 STS1_1 MCLK_1 GND RCLK_1 RPOS_1 RNEG_1 VDD RNEG_0 RPOS_0 RCLK_0 GND MCLK_0 DJA_1/SDI AGND 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 XRT71D03 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 AGND FL_2 STS1_2 DJA_2/CS MCLK_2 GND RCLK_2 VDD RNEG_2 RPOS_2 GND DJA_0/SCLK DS3/E3_0 STS1_0 FL0 AGND ORDERING INFORMATION PACKAGE 64 Pin TQFP OPERATING TEMPERATURE RANGE -40C to +85C 2 ac XRT71D03 3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR REV. 1.2.0 TABLE OF CONTENTS GENERAL DESCRIPTION .................................................................................................. 1 FEATURES ................................................................................................................................................... 1 APPLICATIONS ............................................................................................................................................. 1 Figure 1. Block Diagram of the XRT71D03 ........................................................................................... 1 Figure 2. Pin Out of the XRT71D03 ........................................................................................................ 2 ORDERING INFORMATION ..................................................................................................................... 2 TABLE OF CONTENTS...................................................................................................................................... I PIN DESCRIPTIONS ........................................................................................................... 3 ELECTRICAL CHARACTERISTICS ................................................................................... 9 Figure 3. Input/Output Timing ................................................................................................................ 9 Figure 4. Timing Diagram for the Microprocessor Serial Interface .................................................. 10 SYSTEM DESCRIPTION ................................................................................................... 12 Figure 5. Illustration of a typical Channel_n of the XRT71D03 configured to operate in the Hardware Mode ........................................................................................................................................ 12 Figure 6. Illustration of a typical Channel_n of the XRT71D03 (configured to operate in the Host Mode) ....................................................................................................................................... 13 1.0 Jitter Attenuator PLL .............................................................................................................................. 13 1.1 BACKGROUND INFORMATION DEFINITION OF JITTER ....................................................................................................13 1.2 JITTER TRANSFER CHARACTERISTICS.........................................................................................................................13 Figure 7. Category 1 DS3 Jitter Transfer Mask .................................................................................. 14 1.2.1 Jitter Tolerance .............................................................................................................................................14 1.2.2 Jitter Generation............................................................................................................................................14 1.2.3 Jitter Attenuation ...........................................................................................................................................14 1.3 XRT71D03 JITTER TRANSFER AND TOLERANCE.........................................................................................................15 TABLE 1: XRT71D03 JITTER TRANSFER FUNCTION .................................................................................. Figure 8. DS3 Jitter Transfer Characteristics ..................................................................................... Figure 9. E3 Jitter Transfer Characteristics ........................................................................................ Figure 10. STS-1 Jitter Transfer Characteristics ................................................................................ TABLE 2: XRT71D03 MAXIMUM JITTER TOLERANCE ................................................................................. 2.0 Operating Modes .................................................................................................................................... 15 16 16 17 18 19 2.1 HARDWARE MODE .....................................................................................................................................................19 TABLE 3: FUNCTIONS OF DUAL MODE PINS IN HARDWARE MODE CONFIGURATION ...................................... 19 2.2 HOST MODE.............................................................................................................................................................19 TABLE 4: ADDRESS AND BIT FORMATS OF THE COMMAND REGISTERS ...................................................... 19 3.0 Microprocessor Serial Interface ............................................................................................................ 19 3.1 SERIAL INTERFACE OPERATION..................................................................................................................................19 3.1.1 Bit 1--R/W (Read/Write) Bit ..........................................................................................................................19 3.1.2 Bits 2 through 5--A0, A1, A2, A3, and A4 ....................................................................................................19 3.1.3 Bit 7--A5 .......................................................................................................................................................19 3.1.4 Bit 8--A6 .......................................................................................................................................................19 3.1.5 Read Operation .............................................................................................................................................19 3.1.6 Write Operation .............................................................................................................................................20 Figure 11. Microprocessor Serial Interface Data Structure ............................................................... 20 3.1.7 Simplified Interface Option ............................................................................................................................20 Figure 12. Timing Diagram for the Microprocessor Serial Interface ................................................ 21 ORDERING INFORMATION ............................................................................................. 22 PACKAGE DIMENSIONS ................................................................................................. 22 REVISION HISTORY ..................................................................................................................................... 23 I XRT71D03 3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR REV. 1.2.0 ac PIN DESCRIPTIONS PIN DESCRIPTION PIN # 1 2 3 NAME AVDD GND RRCLK_0 TYPE **** **** O DESCRIPTION Analog Power Supply = 5V5% or 3.3V5% Digital Power Supply = 5V5% or 3.3V5% Received Recovered Output (De-jittered) Clock - channel 0: Output the de-jittered or smoothed clock if the jitter attenuator is enabled. The de-jittered data, RRPOS/RRNEG are clocked to this signal. If RRCLKES is "low", RRPOS/RRNEG will be updated at the falling edge of RRCLK. If RRCLKES is "high", RRPOS/RRNEG will be updated at the rising edge of RRCLK. 4 RRPOS_0 O Received Recovered Positive Data (De-Jittered) Output - channel 0: De-jittered positive data output. Updated on the rising or falling edge of RRCLK, depending upon the state of the RRCLKES input pin (or bit-field setting). 5 RRNEG_0 O Received Recovered Negative Data (De-Jittered) Output - channel 0: De-jittered negative data output. Updated on the rising or falling edge of RRCLK, depending upon the state of the RRCLKES input pin (or bit-field setting). 6 RRCLKES I Received Recovered Clock Edge Select Input: Hardware Mode: 1. When RRCLKES = "0", then RRPOS and RRNEG are updated on the falling edge of RRCLK 2. When RRCLKES = "1", then RRPOS and RRNEG are updated on the rising edge of RRCLK NOTE: This applies to all channels. Host Mode Connect this pin to GND when the 71D03 is configured in the Host Mode. Internal 50 K Ohm pull-down resistor. No Connection 7 8 NC Rest I Reset Input. (Active-Low): A high-low transition will re-center the internal FIFO, and will clear the Command Registers (for Host Mode operation). Resetting this pin may corrupt data within the device. For normal operation, pull this pin to VDD. Internal 50 K Ohm pull-up resistor. DS3/E3 Select Input - channel 1: This pin along with the STS-1 mode select pin selects the operating mode. The following table provides the configuration: XRT71D04 Operating Mode STS-1 DS3/E3 0 0 DS3 (44.736 MHz) 0 1 E3 (34.368 MHz) 1 0 STS-1 (51.84 MHz) 1 1 E3 (34.368 MHz) Internal 50 K Ohm pull-down resistor. 9 DS3/E3_1 I 10 VDD **** Digital Power Supply = 5V5% or 3.3V5% 3 ac PIN DESCRIPTION PIN # 11 NAME MODE_CTRL TYPE I XRT71D03 3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR REV. 1.2.0 DESCRIPTION Mode Control: When "High" in Multimode, all channels are independent. When "Low", the Master Channel (channel0) controls DS3/E3_n, STS1_n, RCLKES, FSS and MCLKn. DJA is NOT affected. Internal 50 K Ohm pull-up resistor. 12 ICT I In Circuit Testing Input. (Active low): With this pin tied to ground, all output pins will be in high impedance mode for in-circuit-testing. For normal operation this input pin should be tied to VDD. Internal 50 K Ohm pull-up resistor. 13 HOST I Host/Hardware Mode Select: An active-high input enables the Host mode. Data is written to the command registers to configure the XRT71D04. In the Host mode, the states of discrete input pins are inactive. An active-low input enables the Hardware Mode.In this mode, the discrete inputs are active. Internal 50 K Ohm pull-down resistor. 14 FLRST I Fifo Limit Reset Hardware Mode Whenever the FIFO is within 2 bits of either underflow or overflow, the FLn) will be set high. This pin allows the user to reset the state of FL_n, (FIFO Limit) output pin. This pin when pulsed "High", resets the the FL_n output pin, (toggles to GND). NOTE: The FL_n could be set "High" again if the FIFO is within 2 bits of either underflow or overflow. Host Mode Reading the FL_n bits in the status registers clears the FL_n pin. Master RESET also clears the FL_n output. This pin is tied to GND. FLRST has no effect in this mode. Internal 50 K Ohm pull-down resistor. 15 16 17 18 GND NC AGND FL_0 **** Digital Ground No Connection **** O Analog Ground FIFO Limit - channel 0: This output pin is driven high whenever the internal FIFO comes within two-bits of being underflow or overflow. 19 STS1_0 I SONET STS1 Mode Select - channel 0: This pin along with the DS3/E3_0 select pin configures the XRT71D03 either in E3, DS3 or STS-1 mode. A table relating to the setting of the pins is given below: XRT71D03 Operating Mode STS-1 DS3/E3 0 0 DS3 (44.736 MHz) 0 1 E3 (34.368 MHz) 1 0 STS-1 (51.84 MHz) 1 1 E3 (34.368 MHz) This input pin is active only in the Hardware Mode 4 XRT71D03 3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR REV. 1.2.0 ac PIN DESCRIPTION PIN # 20 NAME DS3/E3_0 TYPE I DESCRIPTION DS3/E3 Select Input - channel 0: See description pin 8. Internal 50 K Ohm pull-down resistor. 21 DJA_0/SCLK I Hardware Mode Disable Jitter Attenuator Input - Channel 0: An active-high disables the Jitter Attenuator. The RPOS/RNEG and RCLK will be passed through without jitter attenuation. Host Mode Microprocessor Serial Interface Clock Signal: This signal will be used to sample the data on the SDI pin, on the rising edge of this signal. Additionally, during "Read" operations, the Microprocessor Serial Interface will update the SDO output on the falling edge of this signal. Internal 50 K Ohm pull-down resistor. 22 23 GND RPOS_2 **** I Digital Ground Received Positive Data (Jittery) Input: - channel 2: Data that is input on this pin is sampled on either the rising or falling edge of RCLK depending on the setting of the RCLKES pin (pin 10). If RCLKES is "high", then RPOS will be sampled on the falling edge of RCLK. If RCLKES is "low", then RPOS will be sampled on the rising edge of RCLK. Internal 50 K Ohm pull-up resistor. 24 RNEG_2 I Received Negative Data (Jittery) - channel 2: The input jittery negative data is sampled either on the rising or falling edge of RCLK depending on the setting of RCLKES. If RCLKES is "high", then RNEG will be sampled on the falling edge of RCLK. If RCLKES is "low", then RPOS will be sampled on the rising edge of RCLK. This pin is typically tied to the "RNEG" output pin of the LIU. Internal 50 K Ohm pull-up resistor. 25 26 VDD RCLK_2 **** I Digital Power Supply = 5V5% or 3.3V5% Received Clock (Jittery) - channel 2: Clock input RCLK2 should be connected to the recovered clock. Internal 50 K Ohm pull-up resistor. 27 28 GND MCLK_2 **** I Digital Ground Master Clock Input - channel 2: Reference clock for internal PLL. 44.736MHz+/-20ppm or 34.368MHz+/20ppm. This clock must be continuous and jitter free with duty cycle between 30 to 70%. It is permissible to use the EXCLK signal orSTS1 clock. Internal 50 K Ohm pull-up resistor. 29 DJA_2/CS I Hardware Mode Disable Jitter Attenuator Input - Channel 2: See description of pin 25 Host Mode Chip Select Input: An active-low input enables the serial interface. Internal 50 K Ohm pull-down resistor. 30 STS1_2 I SONET STS1 Mode Select - channel 2: See description pin 19 5 ac PIN DESCRIPTION PIN # 31 NAME FL_2 TYPE O XRT71D03 3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR REV. 1.2.0 DESCRIPTION FIFO Limit - channel 2: See description pin 18 Analog Ground Analog Power Supply =55% or 3.3V5% Digital Ground 32 33 34 35 AGND AVDD GND RRCLK_2 **** **** **** O Received Recovered Output (De-jittered) Clock - channel 2: See description of pin 3 36 RRPOS_2 O Received Recovered Positive Data (De-Jittered) Output - channel 2: See description of pin 4 37 RRNEG_2 O Received Recovered Negative Data (De-Jittered) Output - channel 2: See description of pin 5 38 FSS I FIFO Size Select Input: When "High": Selects 32 bits FIFO. When "Low": Selects 16 bits FIFO. Internal 50 K Ohm pull-down resistor. 39 SDO O Serial Data Output: This pin will serially output the contents of the specified Command Register, during "Read" Operations. The data, on this pin, will be updated on the falling edge of the SCLK input signal. This pin will be tri-stated upon completion of data transfer. 40 DS3/E3_2 I DS3/E3 Select Input - channel 2: See description pin 8 Internal 50 K Ohm pull-down resistor. 41 42 43 VDD NC RCLKES **** Digital Power Supply = 5V5% or 3.3V5% No Connection I Received Clock Edge Select Input: Hardware Mode 1. When RCLKES = "0", then RPOS and RNEG are updated on the falling edge of RCLK 2. When RCLKES = "1", then RPOS and RNEG are updated on the rising edge of RCLK NOTE: This applies to all channels. Host Mode Connect this pin to GND when the 71D03 is configured in the Host Mode. Internal 50 K Ohm pull-down resistor. 44 RRNEG_1 O Received Recovered Negative Data (De-Jittered) Output - channel 1: See description of pin 5 45 RRPOS_1 O Received Recovered Positive Data (De-Jittered) Output - channel 1: See description of pin 4 6 XRT71D03 3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR REV. 1.2.0 ac PIN DESCRIPTION PIN # 46 NAME RRCLK_1 TYPE O DESCRIPTION Received Recovered Output (De-jittered) Clock - channel 1: See description of pin 3. Digital Ground Analog Power Supply = 5 V5% or 3.3V5% Analog Ground 47 48 49 50 GND AVDD AGND FL_1 **** **** **** O FIFO Limit - channel 1: See description pin 18 51 STS1_1 I SONET STS1 Mode Select - channel 1: See description pin 19 52 MCLK_1 I Master Clock Input - channel 1: See description pin 28. Internal 50 K Ohm pull-up resistor. 53 54 GND RCLK_1 **** I Digital Ground Received Clock (Jittery) - channel 1: See description of pin 26. Internal 50 K Ohm pull-up resistor. 55 RPOS_1 I Received Positive Data (Jittery) Input: - channel 1: See description of pin 23. Internal 50 K Ohm pull-up resistor. 56 RNEG_1 I Received Negative Data (Jittery) - channel 1: See description of pin 24. Internal 50 K Ohm pull-up resistor. 57 58 VDD RNEG_0 **** I Digital Power Supply = 5V5% or 3.3V5% Received Negative Data (Jittery) - channel 0: See description of pin 24. Internal 50 K Ohm pull-up resistor. 59 RPOS_0 I Received Positive Data (Jittery) Input: - channel 0: See description of pin 23. Internal 50 K Ohm pull-up resistor. 60 RCLK_0 I Received Clock (Jittery) - channel 0: See description of pin 26. Internal 50 K Ohm pull-up resistor. 61 62 GND MCLK_0 **** I Digital Ground Master Clock Input - channel 0: See description pin 28. Internal 50 K Ohm pull-up resistor. 7 ac PIN DESCRIPTION PIN # 63 NAME DJA_1/SDI TYPE I XRT71D03 3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR REV. 1.2.0 DESCRIPTION Hardware Mode Disable Jitter Attenuator Input - Channel 1: See description of pin 25 Host Mode Serial Data Input The address value (of the command registers) or the data value is either Read or Written through this pin. The input data will be sampled on the rising edge of the SCLK pin. Internal 50 K Ohm pull-down resistor. 64 AGND **** Analog Ground 8 XRT71D03 3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR REV. 1.2.0 ac ELECTRICAL CHARACTERISTICS AC Electrical Characteristics Electrical Characteristics (TA = 25C, VDD = 3.3 V t0 5.0 V 5% unless otherwise specified) SYMBOL MClk MClk MClk MClk RClk RClk RClk tsu th td te Duty Cycle Frequency E3 + 20 ppm Frequency DS3 + 20 ppm Frequency STS-1 + 20 ppm Duty Cycle Rise Time Fall Time RPOS/RNEG to RClk rise time setup RPOS/RNEG to RClk rising hold time RRPOS/RRNEG delay from RRClk rising RRPOS/RRNEG delay from RRClk falling 3 1 2 2 3 3 5 5 30 PARAMETER MIN 30 TYP 50 34.368 44.736 51.84 50 70 5 5 MAX 70 UNITS. % MHz MHz MHz % ns ns ns ns ns ns FIGURE 3. INPUT/OUTPUT TIMING tsu RCLK th RPOS/RNEG RPOS/RNEG RClkES = 0 RCLK td tsu RCLK th RPOS/RNEG RPOS/RNEG RClkES = 1 RCLK te 9 ac XRT71D03 3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR REV. 1.2.0 Microprocessor Serial Interface Timing ( see Figure 4 ) Electrical Characteristics (TA = 25C, VDD = 3.3 V t0 5.0 V 5 % unless otherwise specified) SYMBOL t21 t22 t23 t24 t25 t26 t27 t28 t29 t30 t31 t32 PARAMETER CS Low to Rising Edge of SClk Setup Time SClk to CS Hold Time SDI to Rising Edge of SClk Setup Time SDI to Rising Edge of SClk Hold Time SClk "Low" Time SClk "High" Time SClk Period SClk to CSB Hold Time CS "Inactive" Time Falling Edge of SClk to SDO Valid Time Falling Edge of SClk to SDO Invalid Time Falling Edge of SClk, or rising edge of CS to High Z 100 MIN 50 20 50 50 240 240 500 50 250 200 100 TYP MAX UNITS. ns ns ns ns ns ns ns ns ns ns ns ns FIGURE 4. TIMING DIAGRAM FOR THE MICROPROCESSOR SERIAL INTERFACE t29 CS t22 SClk t23 SDI t24 R/W A0 A1 t25 t21 t27 t26 t28 CS SClk t30 SDO Hi-Z D0 t31 D1 Hi-Z t33 D2 D7 t32 SDI 10 XRT71D03 3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR REV. 1.2.0 ac DC Electrical Characteristics (TA = 25 C, VDD = 3.3 V 5% unless otherwise specified) PARAMETER Power Supply Voltage Input High Voltage Input Low Voltage Output High Voltage @ IOH=-5mA Output Low Voltage @ IOL=5mA Supply Current (E3) @VDD = 3.465V Supply Current (DS3) @VDD = 3.465V Supply Current (STS-1) @VDD = 3.465V Input Leakage Current (except Input pins with Pull-up resistor). Input Capacitance Output Load Capacitance SYMBOL VDD VIH VIL VOH VOL Icc Icc Icc IL CI CL 5.0 25 75 95 105 MIN 3.135 2.0 -0.5 2.4 0.4 85 109 120 10 A pF pF TYP 3.3 MAX 3.465 5.25 0.8 UNITS V V V V V mA mA DC Electrical Characteristics (TA = 25 C, VDD = 5.0 V 5% unless otherwise specified) PARAMETER Power Supply Voltage Input High Voltage Input Low Voltage Output High Voltage @ IOH=-5mA Output Low Voltage @ IOL=5mA Supply Current (E3) @VDD = 5.25V Supply Current (DS3) @VDD = 5.25V Supply Current (STS-1) @VDD = 5.25V Input Leakage Current (except Input pins with Pull-up resistor). Input Capacitance Output Load Capacitance SYMBOL VDD VIH VIL VOH VOL Icc Icc Icc IL CI CL 5.0 25 120 145 160 MIN 4.75 2.0 -0.5 2.4 0.4 136 160 180 10 A pF pF TYP 5.0 MAX 5.25 5.25 0.8 UNITS V V V V V mA mA ABSOLUTE MAXIMUM RATINGS: Supply Range ESD Rating Operating Temperature Storage Temperature -0.5 V to + 6.0 V > 2000 V on all pins -400C to +850C -65C to + 150C 11 ac SYSTEM DESCRIPTION The XRT71D03 is an integrated 3-channel E3/DS3/ STS-1 jitter attenuator that attenuates the jitter from the input clock and data. The jitter attenuation performance meets the latest specifications such as Bellcore GR-499 CORE,GR-253 CORE, ETSI TBR24,ITU-T G.751,ITU-T G.752 and ITU-T G.755 standards. In addition, the XRT71D03 also meets both the mapping and pointer adjustment jitter generation criteria for both Category I and Category II interfaces as specified in Bellcore GR-253. XRT71D03 3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR REV. 1.2.0 The XRT71D03 also meets the DS3 wander specification that apply to SONET and asynchronous interfaces as specified in the ANSI T1.105.03b 1997 standard. Additionally, to support loop-timing applications, the XRT71D03 can also be used to reduce and limit the amount of jitter in the recovered line clock signal. Figure 5 presents a simple block diagram of the XRT71D03, when it is configured to operate in the Hardware Mode and Figure 6 presents a simple block diagram of the XRT71D03, when it is configured to operate in the Host Mode. WARE FIGURE 5. ILLUSTRATION OF A TYPICAL CHANNEL_N OF THE XRT71D03 CONFIGURED TO OPERATE IN THE HARDMODE ICT DJA_n RClk_n RCLKES RPOS_n RNEG_n FSS HOST Rest DS3/E3_n Jittery Clock Timing Control Block / Phase locked Loop MCLK_n Smoothed Clock Write Clock Read Clock RRCLK_n RRPOS_n RRNEG_n RRCLKES FL_n 16/32 Bit FIFO 12 XRT71D03 3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR REV. 1.2.0 ac FIGURE 6. ILLUSTRATION OF A TYPICAL CHANNEL_N OF THE XRT71D03 (CONFIGURED TO OPERATE IN THE HOST MODE) ICT Jittery Clock Timing Control Block / Phase locked Loop MClk_n Smoothed Clock RCLK_n Write Clock Read Clock RRCLK_n RRPOS_n 16/32 Bit FIFO RPOS_n RNEG_n RRNEG_n RRCLKES FL_n HOST Reset Microprocessor Serial Interface CS SDI SDO SClk The XRT71D03 DS3/E3 Jitter Attenuator IC consists of the following functional blocks: * The Jitter-Attenuator PLL * Timing Control Block * The 2-Channel 16/32 Bit FIFO * Serial Microprocessor Interface 1.0 JITTER ATTENUATOR PLL 1.1 BACKGROUND INFORMATION DEFINITION OF JITTER from their ideal positions in time. Jitter can occur due to any of the following: 1) Imperfect timing recovery circuit in the system 2) Cross-talk noise 3) Inter-symbol interference/Signal Distortion 1.2 JITTER TRANSFER CHARACTERISTICS The primary purpose of jitter transfer requirements is to prevent performance degradations by limiting the accumulation of jitter through the system such that it does not exceed the network interface jitter requirements. Thus, it is more important that a system meet the jitter transfer criteria for relatively high input jitter amplitudes. The jitter transferred through the system must be under the jitter mask for any input jitter amplitude within the range as shown in Figure 7 One of the most important and least understood measures of clock performance is jitter. The International Telecommunication Union defines jitter as short term variations of the significant instants of a digital signal 13 ac XRT71D03 3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR REV. 1.2.0 FIGURE 7. CATEGORY 1 DS3 JITTER TRANSFER MASK 0.1 Jitter Gain (dB) slope = -20 dB/decade Acceptable Range 40 Frequency (Hz) 1.2.1 Jitter Tolerance The jitter tolerance in the network element is defined as the maximum amount of jitter in the incoming signal that it can receive in an error-free manner. 1.2.2 Jitter Generation Jitter generation is defined in Section 7.3.3 of GR499-CORE. Jitter generation criteria exists for both Category I and II interfaces, which consist of mapping and pointer adjustment jitter generation. Mapping jitter is the sum of the intrinsic payload mapping jitter and the jitter that is generated as a result of the bit stuffing mechanisms used in all of the asynchronous DSn mapping into STS SPE. 1.2.3 Jitter Attenuation A digital Jitter Attenuation loop combined with the FIFO provides Jitter attenuation. The Jitter Attenuator requires no external components except for the reference clock. Data is clocked into the FIFO with the associated clock signal (TClk or RClk) and clocked out of the FIFO with the dejittered clock and data. When the FIFO is within 2 bits of being completely full, the FIFO Limit (FL) will be set. In Figure 5 and Figure 6, this de-jittered clock is labeled Smoothed Clock. This Smoothed Clock is now used to Read Out the Recovered Data from the 16/32 bit FIFO. This Smoothed Clock will also be output to the Terminal Equipment via the RRClk output pin. Likewise, the Smoothed Recovered Data will output to the Terminal Equipment via the RRPOS and RRNEG output pins. The XRT71D03 is designed to work as a companion device with XRT73L03 (STS-1/DS3/E3) Line Interface Unit. ETSI TBR24 specifies the maximum output jitter in loop timing must be no more than 0.4UIpp when measured between 100Hz to 800KHzwith up to 1.5UI input jitter at 100Hz. This means a jitter attenuator with bandwidth less than 100Hz is required to be compliant with the standard. ITU G.751 is another application where low bandwidth jitter attenuator is needed to smooth the gapped clock output in the de-multiplexer system. 14 XRT71D03 3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR REV. 1.2.0 ac Table 2 summarizes the results of jitter tolerance testing, performed on the XRT71D03. Graphs of the measured Jitter Transfer are shown in Figure 8, Figure 9 and Figure 10. 1.3 XRT71D03 JITTER TRANSFER AND TOLERANCE Table 1 summarizes the results of jitter transfer characteristics testing, performed on the XRT71D03. TABLE 1: XRT71D03 JITTER TRANSFER FUNCTION APPLICATION INPUT JITTER FREQ. (HZ) 10 20 30 40 50 60 80 100 125 150 200 300 500 >1000 2000 3000 5000 1UIPP DS3 10UIPP 1UIPP E3 10UIPP 1UIPP STS-1 10UIPP Jitter Gain (dB) -0.10 -2.04 -3.63 -5.98 -7.55 -9.57 -12.54 -14.67 -16.67 -17.32 -18.77 -21.43 -22.22 -25.42 -0.30 -2.24 -4.33 -6.16 -7.82 -9.17 -11.28 -13.36 -14.91 -16.78 -18.96 -21.81 -26.09 -33.44 Jitter Gain (dB) -0.15 -3.16 -5.51 -7.68 -10.36 -12.50 -15.20 -16.22 -17.38 -19.45 -20.36 -22.96 -23.78 -23.51 -0.22 -3.24 -5.93 -7.99 -9.61 -11.27 -13.59 -15.51 -17.07 -18.75 -21.11 -24.46 -28.84 -35.77 Jitter Gain (dB) 0.22 -0.69 -5.92 -8.10 -10.17 -11.24 -13.65 -14.78 -16.94 -17.38 -19.57 -21.96 -23.59 -25.76 -26.27 -27.41 -26.15 0.53 -1.09 -3.01 -4.74 -6.33 -7.64 -9.98 -11.92 -13.75 -15.23 -17.41 -21.69 -25.47 -32.99 -39.83 -41.95 -44.16 15 ac XRT71D03 3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR REV. 1.2.0 FIGURE 8. DS3 JITTER TRANSFER CHARACTERISTICS DS3 Jitter Transfer 10 5 0 -5 Jitter Gain (dB) -10 -15 -20 -25 -30 -35 -40 Frequency (Hz) 1UIpp 10UIpp Mask 100 1,000 FIGURE 9. E3 JITTER TRANSFER CHARACTERISTICS E3 Jitter Transfer 10 5 0 -5 Jitter Gain (dB) -10 -15 -20 -25 -30 -35 -40 Frequency (Hz) 1UIpp 10UIpp Mask 100 1,000 16 XRT71D03 3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR REV. 1.2.0 ac FIGURE 10. STS-1 JITTER TRANSFER CHARACTERISTICS STS-1 Jitter Transfer 10 5 0 -5 -10 Jitter Gain (dB) -15 -20 -25 -30 -35 -40 -45 -50 Frequency (Hz) 1UIpp 10UIpp Mask 100 1,000 10,000 17 ac XRT71D03 3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR REV. 1.2.0 TABLE 2: XRT71D03 MAXIMUM JITTER TOLERANCE APPLICATION FIFO SIZE FREQ. (HZ) 10 20 30 40 50 60 80 100 125 150 200 300 500 >1000 16 DS3 32 16 E3 32 16 STS-1 32 UI (PEAK TO PEAK) 34.313 21.439 18.314 16.939 16.314 16.064 15.689 15.439 15.439 15.314 15.314 15.189 15.189 15.0189 >64 43.188 36.813 34.313 33.188 32.563 31.814 31.439 31.314 31.189 31.064 30.939 30.939 30.939 UI (PEAK TO PEAK) 26.689 18.564 16.689 16.064 15.689 15.564 15.314 15.314 15.189 15.189 15.189 15.064 15.064 15.189 53.313 37.438 33.938 32.688 32.063 31.689 31.314 31.189 31.064 31.064 30.939 30.939 30.939 30.939 UI (PEAK TO PEAK) 38.938 22.689 18.939 17.439 16.814 16.439 16.064 15.814 15.689 15.689 15.564 15.564 15.564 15.439 15.439 15.439 15.439 >64 44.813 37.688 34.938 33.563 32.813 32.063 31.814 31.564 31.439 31.314 31.189 31.189 31.189 31.189 26.189 16.189 18 XRT71D03 3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR REV. 1.2.0 ac 2.2 HOST MODE In Host mode (connect the HOST pin to VDD), the serial port interface pins are used to control configuration and status report. In this mode, serial interface pins, SDI, SDO,SCLK and CS are used. A listing of these Command Registers, their Addresses and their bit-formats are listed below in Table 4. 2.0 OPERATING MODES 2.1 HARDWARE MODE The HOST pin is used to select the operating mode of the XRT71D03. In Hardware mode (connect this pin to ground), the serial processor interface is disabled and hard-wired pins are used to control configuration and report status. TABLE 3: FUNCTIONS OF DUAL MODE PINS IN HARDWARE MODE CONFIGURATION PIN # 63 21 29 PIN NAME DJA_1/(SDI) DJA_0/SCLK DJA_2(CS) FUNCTION, WHILE IN THE HARDWARE MODE DJA_1 DJA_0 DJA_2 TABLE 4: ADDRESS AND BIT FORMATS OF THE COMMAND REGISTERS ADDR 0X06 0x07 0x0E 0x0F 0x16 0x17 COMMAND REGISTER CR6 CR7 CR14 CR15 CR22 CR23 TYPE R/W RO R/W RO R/W RO D7 *** *** *** *** *** *** D6 *** *** *** *** *** *** D5 STS-1_0 *** STS-1_1 *** STS-1_2 *** D4 DS3/E3_0 *** DS3/E3_1 *** DS3/E3_2 *** D3 D2 D1 D0 FSS_0 FL_0 FSS_1 FL_1 FSS_2 FL_2 DJA_0 RRClkES_0 RClkES_0 *** *** DJA_1 RRClkES_1 RClkES_1 *** *** DJA_2 RRClkES_2 RClkES_2 *** *** 3.0 MICROPROCESSOR SERIAL INTERFACE The serial interface for the XRT71D03 and the XRT73L00 family of E3/DS3/STS-1 LIU's are the same, which makes it easy to configure both the XRT71D03 and the LIU with a single CS, SDI, SDO and SClk input and output pins. 3.1 SERIAL INTERFACE OPERATION. Serial interface data structure and timings are provided in Figure 5 and 6 respectively. The clock signal is provided to the SClk and the CS is asserted for 50 ns prior to the first rising edge of the SClk. 3.1.1 Bit 1--R/W (Read/Write) Bit This bit will be clocked into the SDI input, on the first rising edge of SClk (after CS has been asserted). This bit indicates whether the current operation is a Read or Write operation. A "1" in this bit specifies a Read operation, a "0" in this bit specifies a Write operation. 3.1.2 Bits 2 through 5--A0, A1, A2, A3, and A4 19 The five (5) bit Address Values (labeled A0, A1, A2, A3, and A4). The next five rising edges of the SClk signal will clock in the 5-bit address value for this particular Read (or Write) operation. The address selects the Command Register for reading data from, or writing data to. The address bits to the SDI input pin is applied in ascending order with the LSB (least significant bit) first. 3.1.3 Bit 7--A5 A5 must be set to "0", as shown in Figure 11. 3.1.4 Bit 8--A6 The value of A6 is a don't care. Once these first 8 bits have been written into the Serial Interface, the subsequent action depends upon whether the current operation is a Read or Write operation. 3.1.5 Read Operation Once the last address bit (A4) has been clocked into the SDI input, the Read operation will proceed through an idle period, lasting three SClk periods. On ac the falling edge of SClk Cycle #8 (see Figure 11) the serial data output signal (SDO) becomes active. At this point the user can begin reading the data contents of the addressed Command Register (at Address [A4, A3, A2, A1, A0]) via the SDO output pin. The Serial Interface will output this eight bit data word (D0 through D7) in ascending order (with the LSB first), on the falling edges of the SClk. The data (on the SDO output pin) is stable for reading on the very next rising edge of the SClk. XRT71D03 3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR REV. 1.2.0 3.1.6 Write Operation Once the last address bit (A4) has been clocked into the SDI input, the Write operation will proceed through an idle period, lasting three SClk periods. Prior to the rising edge of SClk Cycle #9, the eight bit data word is applied to SDI input. Data on SDI is latched on the rising edge of SClk. FIGURE 11. MICROPROCESSOR SERIAL INTERFACE DATA STRUCTURE CS SClk SDI SDO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 R/W A0 A1 A2 A3 A4 0 A6 D0 D1 D2 D3 D4 D5 D6 D7 High Z D0 D1 D2 D3 D4 D5 D6 D7 High Z NOTES: 1. 2. 3. 4. A5 is always "0". R/W = "1" for Read Operations R/W = "0" for Write Operations Denotes a "don't care" value (shaded areas) 3.1.7 Simplified Interface Option The user can simplify the design of the circuitry connecting to the Microprocessor Serial Interface by tying both the SDO and SDI pins together, and reading data from and/or writing data to this combined signal. This simplification is possible because only one of 20 XRT71D03 3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR REV. 1.2.0 ac these signals are active at any given time. The inactive signal will be tri-stated. FIGURE 12. TIMING DIAGRAM FOR THE MICROPROCESSOR SERIAL INTERFACE t29 CS t22 SClk t23 SDI t24 R/W A0 A1 t25 t21 t27 t26 t28 CS SClk t30 SDO Hi-Z D0 t31 D1 Hi-Z t33 D2 D7 t32 SDI 21 ac ORDERING INFORMATION PART # XRT71D03IV THERMAL INFORMATION PACKAGE 64 Pin TQFP Theta - JA = 38 C/W XRT71D03 3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR REV. 1.2.0 OPERATING TEMPERATURE RANGE -40oC to +85oC Theta JC = 7 C/W PACKAGE DIMENSIONS 64 Lead Thin Quad Flat Pack (10 x 10 x 1.4 mm LQFP) SYMBOL A A1 A2 B C D D1 e L aaa INCHES MIN MAX 0.055 0.063 0.002 0.006 0.053 0.057 0.007 0.011 0.004 0.008 0.465 0.480 0.390 0.398 0.0020 BSC 0.018 0.050 0 7 7 typ 0.003 MILLIMETERS MIN MAX 1.40 1.60 0.05 0.15 1.35 1.45 0.17 0.27 0.09 0.20 11.80 12.20 9.90 10.10 0.05 BSC 0.45 0.75 0 7 7 typ 0.08 Note: Control Dimensions are the Millimeter Column 22 XRT71D03 ac 3 CHANNEL E3/DS3/STS-1 JITTER ATTENUATOR REV. 1.2.0 REVISION HISTORY Rev. P1.0.1; Revised pull-up/pull-down resistors on various pins. Rev. P1.0.2; Changed date and made minor edits to page 1. Rev. P1.0.3; Corrected Pin List descriptions. Modified pin names to be consistent, ie MCLK0, RPOS0, RNEG0, etc. changed to MCLK_0, RPOS_0, RNEG_0, etc. Changed VSS to GND. Changed figures to reflect pin name changes. Rev. 1.1.0 Removed preliminary designation. Added electrical tables. Rev. 1.1.1 Corrected Table 4 adding RRClkES_n as data D2, STS-1_n as D5, added D7. Corrected the description of the section 3 Serial Microprocessor Interface. Moved figure 9 into Electrical Characteristics Section. Moved Jitter Transfer/Tolerance tables into Jitter Attenuator Section 1. Edited electrical tables. Rev. 1.1.2 Corrected ordering information from XRT71DO3 to 71D03IV. Rev. 1.2.0 Removed all reference to STS-1 to DS3 desynchronizer. NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 2001 EXAR Corporation Datasheet September 2001. Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited. 23 |
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